[svlug] j-core vs RISC-V

[Ivan Sergio Borgonovo]

On 05/08/2017 07:32 AM, Rob Landley wrote:
> On 05/06/2017 06:35 AM, Ivan Sergio Borgonovo wrote:
>> I don't know about architecture advantage of j-core vs RISC-V but
>> considering j-core is just on FPGA but you can buy real RISC-V and
>> considering who's behind RISC-V I'd bet on RISC-V.
>
> J-core is working with artanalog on first silicon:
>
>   http://lists.j-core.org/pipermail/j-core/2017-March/000558.html
>
> I usually describe risc-v vs j-core vs as being a lot like Pascal vs C.
> One was a large group of academics coming up with "the right way to do
> it" without any specific use case in mind, let alone dogfooding. The
> other was a small team of engineers making a tool for their own use and
> refining it as they used it.

So, did I get it wrong?
Who's C and who's Pascal?
Did I get anything else wrong?

Now I expect you say j-core is C. So I wonder why you felt the need of a 
"new" tool and what is your "own use".

I've read the j-core home more carefully and I got j-core is not only 
inspired but is compatible with SuperH.
This fact and the fact that it can already run Linux put it in a much 
better place than I thought.

Do you think there is any chance to see large deployment of Linux on a 
new architecture?

-- 
Ivan Sergio Borgonovo
http://www.webthatworks.it http://www.borgonovo.net